Data separation circuitry for reading information from a moving support

ABSTRACT

An internally clocked digital circuit for decoding double frequency data. A first counter develops a count representative of the elapsed time between two adjacent timing pulses in the signal train. Upon detecting the second of the two adjacent timing pulses, that count is loaded into a second counter. The second counter is stepped at a higher frequency than the first counter to provide an output signal after counting said count. The output signal of the second counter is used to load data signals into a deserializer, and to identify the next timing pulse in the signal train. Also, means for generating sequential control signals for controlling the resetting of the counters and loading the count from the first counter into the second counter with each timing pulse in the signal train, and for ignoring initial signals in the signal train.

United States Patent 1191 Fiehmann et al.

45 Jan. 7, 1975 [75] Inventors: Donald E. Fiehmann, San Jose; Kim

C. Reynolds, San Martin, both of Calif.

[73] Assignee: International Business Machines, Armonk, N.Y.

[22] Filed: Dec. 26, 1973 21 Appl. NO.: 428,582

[52] U.S. Cl. 235/61.l1 D, 235/6l.11 E, 328/63, 329/107, 360/43 3,711,843 4/1971 Galvagni.... 360/43 3,750,108 2/1971 Jensen 340/1725 3,806,706 4/1974 Hasslinger e al.... 235/6l.ll E 3,811,033 5/1974 Herrin et al 235/6l.l1 E

Primary Examiner-Daryl W. Cook Attorney, Agent, or Firm-Shelley M. Beckstrand [57] ABSTRACT An internally clocked digital circuit for decoding double frequency data. A first counter develops a count representative of the elapsed time between two adjacent timing pulses in the signal train. Upon detecting the second of the two adjacent timing pulses, that count is loaded into a second counter. The second counter is stepped at a higher frequency than the first counter to provide an output signal after counting said count. The output signal of the second counter is used to load data signals into a deserializer, and to identify the next timing pulse in the signal train.

Also, means for generating sequential control signals for controlling the resetting of the counters and loading the count from the first counter into the second counter with each timing pulse in the signal train, and for ignoring initial signals in the signal train.

6 Claims, 3 Drawing Figures Patented Jan. 7, 1975 3,859,510

3 Sheets-Sheet 1 Patented Jan. 7, 1975 3,859,510

3 Sheets-Sheet 2 RESET SHIFT COU LOAD SHIFT A COUNTER 51 A RESET SHIFT SHIFT LATCH FIG. 2

Patented Jan. 7, 1975 3 Sheets-Sheet 5 T 8 w x mm: W T ON 5% T 22 a 23 I m T 2:31

ATA SEPARATION CIRCUITRY counter must be capable of counting up and down, and

INFORMATION FROMA MOVING SUPPORT is thus significantly more complicated than a simple unidirectional counter.

f .l'riall of these prior art devices for decoding variable BACKGROUND OF velocity data signals, the decoding circuitry requires l. Field of the Invention a v J complicated analog components, comparators, or upl- This invention relates to the readoutofinfo'rmation down" (bidirectional) counters. There exists, therefore, {from an element requiring relative movement between a need for a low cost, highly reliable decoding circuit .theelement and a transducer. The element Imay b 1' which significantly reduces the number and complexity magnetically encoded, for example, with information of the .components, and which can be packaged in a low andtiming signals interspersedin a double-frequency. cost, hand driven-card reader as in terminal devices de: .-,The -relative movement may result from 'rnoving: forfretail, banking, inventory and other similar systems. eithei t ej-elementor the transducer.

1 fzj-gngsejri rion of the Prior Art t f S M Y OF H INVENTION -iThe doubleifrequency code, sometimes referred toas'fl'S 2f By waylof summary, the invention comprises an ap- "F/-2 E, is;well k ownin the art. This code is the same as: "@paratus and method for decoding double frequency en- ..a'p'ulserat em dulationcode with a 2:1 pulse rate ratio...) "coded-data where timing pulses interspersed with data In' these-codes; cloclE {and data signals are interleaved "pulsesareirecorded on'a medium. During readback, such that eachgdata signal appears between two adja-' j dataflisignals'read from the 'mediumare separated from cent clock .signals-andpwhere; each'data signal is sepatheclocl1signals ajndjassembled into characters for subrated'by oneor more clocklsignal's'. Many circuits have sequent utilization,,First counter means, driven by a 5 been pro deg for separatin'g'the data signalsfr'om the highgfrequenc'y oscillator,-develops a count representaclock-signals, with most of them requiring extremely, tiveIofi-tli'efelapsed time (roughlyrepresen'tative of the f clo's'eftolraneeslon the frequency of the signal train in distance'IQBetvveeritWo adjace'ntclock signals..' A second forder to synehro'ni zethat signal .trainlwith an oscillator counteris loaded with the contents of the first counter qr-interval ocl whi'ch-co'n'trolsthe decoding or sepa- (or. 1 the a ple-wens, depending upon the. type of i'ration circu t; D I counter used)juponfdetectingthe occurrence of the I i I and; m etl iods'haveQbjeen. provided for, 3 second of sai djacent clock signals. The second ta signals from .a signal train where the counterthen i s driven at a'hig'her frequency. than; said ibjeetf to widevariationsaswhen first counter 10 provide anloutputf signal after counting ency data' encoded in a magnetic wh'ere thecard o'r-th'e rielzidhead/ mair of eapgc'i'reisigeaireii oustfio adjacent leclepulseSL'Latch means, controlled .theclo'ck to clock ,r data: signal before nddetectand. presence of a- {raw clockand,dataisignalastream, fqontrolsfth loadi g 5 sive and relatively;

- Exemplaryjio'fdi-g -controlsfthei resetting and thefeounter's;

tagesoftheinverition will be a psr nrr em: the following rnore', particularfdescriptionf.of preferred embodilil G li-is abl oclc diagram of thel ulser Ignore cuit tr o;

FIG. :1 isatimin'g eha uilts of no land lory,

i yaj'series of scribed more fu lly i'n connection-with FIG. 2. This cirtection of each clock ortiming pulse appearing on the input line]; followingl the firstfew' signals, which are to theivaluecountedby s aid first counter, such that said signal occurs afterifthlefsejcond clocksignal' at fractionv of t v ime elapsedjbetwe'e'nsaid previi.

nately cha dind d'isc-hargedfat different 'rate s-totime' byfs'aid foutput'signahj identifiesthe, cloekf pulse in the" loclg in; tlie signal trai ri' td f ofljdatajpuglsesinto:aydeserialiiingi'shift'register, and

The foregoingand other ob jects', tie atures jandadvan- 'e-lnventiomas-illustra dinzthe a'ccompany- Q I G; Tisha bloc'kdiagram oi' applicanjts data separ'ag states of selected a components duringiane templary-operation 'of the, 'e ir Resti g-goats he dia'wlji igs', a aeraiiu'desieri inehj 1 ill be giv'enfofi -ipreferredembodiments of the inven I ".chronizing circuitisproyi'ded.for decodirig variable fre-- Referring HQ.lithe majon'components include;

cujt operates togenratelagseriesof timing pulsesf t i,

45, 46; and 47 asfshownin FIG. SrThese pulses control gthe. resetting and-,"shiftin'g'of thewarious counters-aridi' .jlatch es,'" and-aref generated in'connection with m ats; i

UP Counter 20 and Shift Counter 24, in connection 28 are the set outputs of Shift Latch 26 on line'2l and r a with the load gates 22, operate under control of the osthe Any Pulser signal on line 33. The output of AND ,cillator and Divide circuit 14 to generate a count gate 28 is provided along line 19 to OR invert circuit representing-the clock to clock timing in the signal 16. ,t'r'ain online 13 and for operating the data separation 5 Herein, Divide circuit 14 is a divide by three circuit latches 2'6 and 43; Serializer-deserializer 34 assembles r idi one l e into the first st e of Shift co n r 1 a; i the information pulses into characters for transference 24 f h three l k pulses or i l transitions I C ftO the -utilizationdevice (not shown) along lines 39. pearing n line and gated through 0] 18 Such 3 ir.

A m detailedidescription will now be givfin of cuit is described at page 272 of The Texas Instruments 1:2 i Transdblcef 15 P g a read Signal from for exam- 10 Components Groups publication Designing with TTL "sk magnetically r Optically-encoded card or tape, integrated Circuits, copyright 1971. Similarly, each of t h i amplified P i the transducer output the various counters, latches, AND, and OR gates,

naly' h wn 'n S P i i SERDES registers, shapers, and transducers shown are mp QP l Q h? s alonglme 13 to readily available components well known to those Pulserandlgnore circuit 40. Aninternal clock or oscil- 5 Skilled in the an :3, latingibirfiif 1.0 has: its ip?- dn lines '11 to An overflow from Shift Counter 24 appearing on line it: n r id gn r W "a dEO' QQ L 41 sets Shift Latch 26, which is reset by an output on UP Counter comprises fi'vestages, as shown.-

P 3 1 a 7 Reset Shift and Data Latches line 31. The set output of 5? R 9? Shift P PQQMP Pillsereand 20 Shift Latch 26 is fed r AND gate 28, to ORlnvert gate i'i, t g f z z g fizfg iifiFBfi iTZ fiffili 18, and back into Pulser and Igncge cigcuit .40, as well t h ft th tt fSER ES 4.Wh Shf Pulser andlgnQFe is fcdalQngfinYe tobad iirfh aaa mit s; utput on line for r r is air: I gates 22. ThelReset U P C ounte r output oflg'nore cirinput to D w, the other input being the Q t :is fed along line 2710-11116,01111118r The Reset pearance of Any Pulse on line 33The output of AND Y- D Latches W of the Pi q 25 30 sets Data Latch 32 which is reset bya pulse on line I .Pulser'and Ignore circuit 40'is red along line 33a) AND 32 l;. PP? Qf- P P. fmm

.'-. aresij28 and.30. Y f- J k he a" 2555;2 2:522:first,12am? it's: vides clocking pulses alonglines ll to OR'lnvert cir-ufl 3 j ,9 A 3 p cuits 16 and 18and Pulser and Ignore circuit 40; A F 25 d, 3 3 F1 a signal r ,:the:sh1ft counter-24m allzeroes. Them-the signal on a '.Ili ne ZS caiises'transfer of theones complementof the qherern b wa ofexam le and not limitation, with each a r, stage coi npri sing a flip fl'op. {The firsttwostag es form contents Qfthe'IU-P counter to the Shft Counter 24 adivide by four circuit, and the high order stages dea velop the clock to clock countfORinvertcircuit 16 ,feeds'the first stage,- and reset UP counter line 27; is

' provi'ded for resettingfall of the stages to-zero. Load th rough'theLo'akglGates122,1JPv Counter 20i'is then; 3 reset to zero by alsi'gnal on line 2171. Finally, Shift Latch ".26v andDataLatchE32arB,reset by asignal on line 31. Nhen-Sl'iift- Latch 26fisset, line 21 .ispositive', thus;

gates 22 comprise AND invertcircuits 68,.each o fli f l 11 Q f bb o p i "Providing- Positive output when both of itsjinp its are s-m'p s v de C r ui 14- Conversely, when Shift T negative. L ad Shift'counter line 25 forms one .inP I t-to i t j i fifi wn: us fl -W oscilla puts of stages il V provide the'other input. D ide'circu'it 1.4;. r

' Shift-Counter 24 comprises'three stages, each stageA f' Shlft ;L h n ABY fi fi j l 3 l f 7 being aflip-flop Of course;more stages may'be pro ml ifiisgn l 91 b k?Y 9 P1 t I v vided. on rrrverr'eir'eu r1s. provides one inputto Di t n g ing o U -cqunte ylt -by e u -1 vide circuit14, withthe other iriputbeingtheoutput-of o h ANDZ8 5m 'm 'rf fi i e t a 1 {ANDInverte'ireuir'esand-ne 'rshirrce rrr r 2;;,- h 5- first-stage ofShiftCounter-24is fed-bytheoutputofthe' P Co n r Divide circuit 14and'AND-flrivert'circuit-66.Stagell .16f isIallOWBd, passing os' cillator:v 'pul sesthroug'hjto;

f-UP' Counter 20' counts u" to-"derive; count-retiree of: Shift Register24 has asits'jinputs theoutputs'of stage f fljfi lg' 1h?Tim ,jafi l fll f fl W? WFWPP WF. I land of AND Inverter 67, its output being fed-to stage. Pu es on'llne 13,-.Di1rrngthrs time, Shift"Couriter -z rt is: 3 I

III. The other input to stage lllvof Shift-Counter -2 4. is'

, the'output r AND inverter 68,'an'd' thejout'put' 5 fa'sterfrate:thanstages in, v, a d yi 'of U P Counter 12,0,

stage is fedalong line 41 to set' the.ShiftLatch:26; Shift I so as toproviide' Online 511 a "signal setting Shift'Latch I; {Latch 26 is set-by an output from: the'Shift-'Counter. 1 26 af.t r,a t =q 1= 1 '5 acem;-apprerim ly.o along line '4l'and DC, is a reset by the Reset Shift and] the elapsed, time between'the previous adjacentclock 1:."

Data Latch line. 31 The set outputvof ShiftLatchq26 is a fed to OR Invert 18 along 11621, to AND gate'28, to appejarsnnlin'e 33,;AND gate30provides a set pulse Pulser and Ignorecircuit 40, andinto SERDES 34. The on lilie'37 'se tting the Date; Ljatch.32-.:llowever, if P i r reset output of Shift Latch 26 is fed along line 35tolonfe Itosetting- ShiftLatch 2 ma a -P l e app n in leg of AND gate 30,:T h e'input to AND ar -30;,is r Barb e-Leena remain inj'th s imode. In either ",pnls'es-on 'line1'3." lflprio r'tojasignal on line 41, pulse Pulser line 33, and its output appears along line 371 to; 5': event, upon receiving an output from ShiftCounter 24 set the Data Latch 32,- Data Latch 32 is reset by a signal setting-Shift Latch '26,,the shift pulse'on line 21 causes n x-Q; on Reset Shift and Data Latch line 31, and its set out the SERDIES shift register 3 4110 shiftand'load into its a put 43 feeds into SERDES 34. The inputs to AND gate z' -lowjorder position the contents of Data Latch 32. I v

'- circuit 28 detects'the beginni clock pulse and inhibits'the counting of UP Counter 20 Thiscauses complementing and loading of the contents of stages Ill through V of UP Counter 20 to the Shift :C'ounter 24g vof stagefllof-UPiCounter 20 to the Divide :byTTh'ree circuit 14, and theresetting of circuits 20, 22 'and24totieroj fjAfni'fore detailed description of the operation of UP Counter,20, Load Latches 22, Divide by Three circuit 1. 14, and Shift'COunter 24 follows. With the appearance o'fila pulse onfline 23,'Divide by Three circuit 14 and sta es i u,.1v,' and v ofupi'co'unte'r 20 are iriverted and loaded linto stages I, ll, andglll; respectively, of Shift ll of U P counter 20 the c'ountdeveloped in UP'Coun'ter 120 is effectively divided by four before being inverted and transferred to the'fShift Counter 24.]Neglectingfbr {the moment; the operation of AND invertf 6 {which countejr 20 this the Divide byThree circuit 14, it will be'seen-that fora-largefnurnber of stages in each of the @Counters 20gand 24,.stage s l, IL andflfliof shift counter -24 are count d as 't arateffaster than 'stags 'IILQI and V of UP; counter 20. Thus; an noverflow' on line 41 "will appear at a timefif'ollowing mock pulse on'li 'n'eg'l3 r 'whichis'eqtial to approximately75 percentjofgth'ejtime elapsed between that clock pulse and the nextfprevi'ous fclock pulse on line 1 3. Nowffor a finite number l .stag'esfirilfthe Up counter 20'fand, shift counter 24,]the, f QQPCISLtlQIl-"OTTAND invert 65 loadin'gfth'e complements,

I "iof t-hei'second stage ',of UP counter 20 intofthe'Divide by Three:circuiti14foperates to more closely appro at 75 percent 'ratio .,However, foria sufficient-1y W her-of stages,'th'at ratio issufficieritly close fiapp ro ated'without,the linclusionof AND-invertc cuit f65,iaridj the setting: 'of,the Divide by Three circuit tog'the' invertje dfcohtents of the second stage f'of,U

' Counter 120. Of course, fanothe'rminorideyiatfion from -{a perfectf 5fpercent relationship is introduced iby' in-j give n U oscillator ltlappea'ringp'n' line'll isfed 'intoTAND Lgate "59.91am Clock' ;and.ffData from fTransducerfl TSfanjd Shaper 12, on line. l'3'is' fedinto-AND gatefitliand'iiito Exclusive Oll c'ircuit 62." The set outputpf Shift hatch -26 appearingonfline 21' is 'fed into AND gates 23,25; I 27; and =31} The inputs to. OR-circirit 5 8; are Power On Reset and Not Photo Cell (T) indicatingthat'a magnetic or opticalcard isnotpresent forsensing-by transt ducer"l-5'. 'The output of vOR circuit 58 resets Ignore I Latch57, thel s'et output of which is fedjinto ANDv gate -59 and the reset output of which is fe,d into AND gate 560,0R circuit 64, 'ar1d the set input otIFlip-Flop 55.

The outputs of AND gates 59 and'60' are fed to fORci'rs ht fist" for 'the duration ,o'f the'Any Pulser signalonfliney33.

of OR gate 8l'is fed to the re 52, 53, and 54. 1

each stage of the S hift' Counter 24 are set to zero. With the: appearance of-"a pulse 'on lir1e:25, thecontents' of i I toggle inputfof Flip-Flop 54, to AND circuits 73 and 75, and through lnverter 76 to AND circuits 72 and 74. The output of Flip-Flop 54 is fed to the toggle input of "Flip-Flop 55, to AND circuits 74 and 75, and through I lnv'ert'er77 to AND circuits 73 and, 72. The output of Flip-Flop 55 is fed to Exclusive OR 62, the output of which is also fed back .to OR circuit 64. The output of ORcircuit 64' is-inverted at Inverter 79 and fed to OR circuit 81,' the otherinput to which is F6. The output set inputs of Flip-Flops 51,

The operation of the circuit of FIG. 2 will next be de- 1 scribed; Withlower On Reset or no document cover{ ing the; lens (PC) -enabling OR circ'uit 58', ignore latch 57 is held-reseL'With Ignore Latch 5 7 reset, AND'gate l :C oui1ter 24. By dropping the; contents of stage's; I and 59 is disabled, blocking passage of oscillator-1 0 pulses :and ANDgate60'isenabled, permitting thefpas sa geof v raw clock anddata pulses1 Als o, w, ith Ignore Latch:57 reset, apositive pulse appears-on one input to OR cir .2 c'uit64. TWi th' An'y, Pulser signal of line- 39 also feeding transfers; thegcomplernentj'of the.secondpstage per 1 OR circuit 64 theoutputl of which 'isinverted', a signal will appear out of OR'81 to-reset Flip-Flops Slthrough -54-o nly WhenrthelghoreLzitch is -set and there is no An yflPulser sig'na lflongline'i 'rigforwhen T ispositive. Th us at Power- 'On Reset,- Counter 50, comprising t v FliprFlops 51-55, is not held either set or reset, andfenabledtorun'. However, as' long as a card is not -.'-u n:der transducer 15, such that thef lensofthe'photo' cell is noi t covered and PC'ispositive,-Counter stages set. 'After a card sensedbeneath the read head and osm l l l t line ,output from AND gate 71 This accomplished by togtive'1going);"toggles 'lilipflilop 51 ,off and Flip-Flopis 5 1 54are held{ reset, andthe' Counter stage "is held goes negative, line isles to experien ce- -five or six chan'gesinstate to permit passage. of initial, poor qualtra'nsitions) before'lgnore Latch 5 7g wi ll beset by an fj 'gling Flip-Flops 5 1and52,1iiider,controlofi'pulses on This occurs inasrnucli as Ignore. Latc'h 57-js in the re'sj' et conditiomx thusenabling AND gate'fifl and disabling-X is fgate'dithroughiANDfcircuit tO;tc IeF1i -F1 p1 5 "j 13 fhas' n oj-effect: The third transition on line- 13: (po's onl The fourth transition on line i3'is ignored-.Thefift transition ou-linelfttoggles Flip-Flop 51 on,'while'Flip- 1 Elopv-52 reniainso condition is decoded in AND" gate 71-[tosetg'lg'nore Latch157gWith Latch 57 set, AND

,gate 60 is deg'ate diand AND-59' isgated-v As the reset wit-180,. the output of which. toggles Flip- Elop sL The output of Flip-Flop 51, is' fed to AND gate 71 :and. to Toggle Flip-Flop 52. The output of Flip1Flop' 52. is \fed to AND gates 71,72; 73,474; 75, and to the toggle input of Flip-Flop 53. The output of Flip-Flop 53 is fed to the fit-54 .5 1

J 'u pm qftat szgaes mi us, audits Pupp 5 g'l'es on positive'ft'rans'itions,:then'Raw Clock and'Dataline l3 is'in-a po'sitive stateL.Thus, ExclusiyeOR '62 is t off, andline ss' sew such that-both inputs to OR 64 .ar'e off, -OR 8,1 {'is} turned onto reset the-" Flip-Flops Raw'Clock andf'Data line -33: through Am at' jsot f1 '7 f o'n'pesifiye goingtrar'isi'tionsi'when line, 13 gassin -,1

OR 62 is turned off causing Flip-Flops ll-54 to be reset.

Thus, counter 50 operates with each signal on line 13. However, as decode logic 72-77 is degated on data transition by Shift Latch output 21 being off, control signals on 23-31 are generated only for clock pulses on line 13.

Any Pulser signal on line 33, however, appears with each transition on line 13 (as seen in FIG. 3). That is, Flip-Flop 55 now toggles sixteen oscillator counts after the last raw clock and data transition. Thus turns off Any Pulser line 33, which is turned on by each transition on line 13.

Thus, Counter 50 cycles for every change in state on line 13 at a rate determined by the frequency of oscillator 11 after the first initial five or six pulses on line 13 have been ignored. AND gates 72-75 in conjunction with inverters 76 and 77 decode the condition of the Flip-Flops 51-54, providing that the Shift Latch is on and a signal present on line 21, to provide Reset Shift Counter signal on line 23, Load Shift Counter signal on line 25, Reset UP Counter signal on line 27, and Reset Shift and Data Latch signal on line 31.

Referring back to FIG. I, with RC line on, Shift Latch 26 is held set. Thus, the first transition on line 113 after Ignore Latch 57 is set (see FIG. 2), is interpreted as a clock pulse, and control signals on lines 23-3I will be generated.

Referring to FIG. 3, the relationship between the amplified data at the transducer 15, the shaped data at line 13, the Any Pulser signal on line 33, the control signals on lines 23, 25, 27, and 31, the output of the Shift Latch on line 35, and the output of the Data Latch on line 43 are shown. The circuit of the invention provides signal 48 on line 35 which is equal in duration to the 75 percent of the time between clock pulses CI and C2. When the signal on line 35 falls, the condition on line 43, representing the outputof the data latch, is shifted into SERDES 34.

While the circuit has been described in connection with a hand driven magnetic encoded card, it will be apparent to those skilled in the art that double frequency data may be encoded in the card in other than magnetic form, such as alternating dark and light spaces. Also, the relative motion between the card and the transducer need not be obtained by driving one or the other by hand, but also mechanically, or by other means. Of course, the circuit of the invention is particularly useful where that relative motion is subject to wide velocity variations, such as in a low quality mechanical device.

In connection with FIG. 1, a shift counter 24 has been described. In this embodiment, the shift counter 24 was loaded with the complement of the contents of UP counter 20 and then incremented to an overflow condition. However, a down counter may be provided as shift counter 24, and the counter 24 loaded directly with the contents of the UP counter 20. An important aspect of the invention is that counter 24 need not be capable of both counting up and down.

According to one aspect of the invention, Pulser and Ignore circuit 40 has been described in connection with Counter 50. Other approaches for generating the con- 6 trol pulses on lines 23-31 in the sequence described in connection with FIG. 3 are apparent. One example would be the use of delay line circuits.

Provided the relative motion between the transducer and the card is constant, there is a direct relationship between distance and time, and between the time or distance between adjacent timing pulses on line 13 and the contents of counter 20, and 24. This is a practical assumption when considering the relationship between adjacent pairs of timing pulses on line 13, inasmuch as instantaneous changes in velocity of the card with respect to the transducer are, in practice, negligible. This, of course, need not be true throughout the pulse train.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

l. Apparatus for recovering data from a double frequency encoded signal train, comprising:

first unidirectional counter means for generating a first count representing the time between adjacent timing signals in said signal train,

second unidirectional counter means responsive to said count for generating an output signal upon counting said first count, means for incrementing said first counter at a first rate and said second counter at a second rate, with said second rate being faster than said first rate,

transfer means responsive to the occurrence of said timing signals for transferring the contents of said first counter to said second counter,

means responsive to said output signal for signalling the presence or absence of a data signal following the second of said timing signals. 2. The apparatus of claim 1, wherein said transfer means loads the complement of the contents of said first counter means into said second counter means, and said second counter means counts up to generate said output signal upon reaching an overflow condition. 3. The apparatus of claim ll, wherein said second counter counts down to generate said output signal upon counting to zero.

4. Apparatus for recovering double frequency encoded data from a record medium, comprising:

transducer means responsive to relative motion of said medium for generating a pulse train of electrical signals including timing pulses and data pulses;

oscillator means for generating clocking pulses, the frequency of said clocking pulses being greater than the frequency of said timing pulses;

first counting means selectively driven by said pulse train of electrical signals and by said clocking pulses,

means responsive to said first counting means deriving a first count representative of the number of initial pulses to be ignored for resetting said first counting means and transferring the control thereof to said clocking pulses;

means responsive to said first counting means when under the control of said clocking pulses for generating a first signal representative of any pulse in second counting means for registering a second count representing the time between adjacent timing pulses in said signal train;

third counting means;

loading means responsive to said second control signal for conditioning said third counting means to count said second number;

means for causing said third counter to count said second number at a faster rate than said second counter;

said third counting means providing a fifth control signal upon counting said second number;

latch means for registering as a data pulse a pulse occurring in said signal train before provision of said fifth control signal,

means responsive to said first control signal for resetting said third counter,

means responsive to said third control signal for resetting said second counter,

means responsive to said fourth control signal for conditioning said latch means to register a subsequent data pulse;

whereby data pulses in said pulse train are detected as those occurring after a timing pulse within a time that represents a fraction of the time between that timing pulse and the next preceding timing pulse where the time between timing pulses is subject to wide variations.

5. In a pulse train decoding system, apparatus for generating control signals comprising:

means for generating a signal train of electrical signals; oscillator means for generating electrical clocking signals,

the frequency of said clocking signals being greater than the frequency of said signal train;

counting means selectively driven by said signal train and by said clocking signals;

means responsive to said counting means deriving a count representative of the number of initial signals in said signal train to be ignored for resetting said counting means and transferring control thereof to said clocking signals; and

means for decoding said counting means when under control of said clocking signals for generating a plurality time sequential control signals.

6. Apparatus for decoding a signal train of double frequency encoded electrical signals, including timing and information signals, comprising:

means for generating high frequency electrical clocking signals,

first dividing means responsive to said clocking signals for generating second clocking signals; second dividing means responsive to said clocking signals for generating third clocking signals,

said third clocking signals having a higher frequency than said second clocking signals;

first unidirectional counting means responsive to said second counting signals for generating a count representing the time between adjacent timing signals; second unidirectional counting means responsive to said third counting signals for generating said count and, thereupon, providing a control signal, detecting means responsive to said control signal for detecting the next timing signal in said signal train and the presence or absence of an information sig- 

1. Apparatus for recovering data from a double frequency encoded signal train, comprising: first unidirectional counter means for generating a first count representing the time between adjacent timing signals in said signal train, second unidirectional counter means responsive to said count for generating an output signal upon counting said first count, means for incrementing said first counter at a first rate and said second counter at a second rate, with said second rate being faster than said first Rate, transfer means responsive to the occurrence of said timing signals for transferring the contents of said first counter to said second counter, means responsive to said output signal for signalling the presence or absence of a data signal following the second of said timing signals.
 2. The apparatus of claim 1, wherein said transfer means loads the complement of the contents of said first counter means into said second counter means, and said second counter means counts up to generate said output signal upon reaching an overflow condition.
 3. The apparatus of claim 1, wherein said second counter counts down to generate said output signal upon counting to zero.
 4. Apparatus for recovering double frequency encoded data from a record medium, comprising: transducer means responsive to relative motion of said medium for generating a pulse train of electrical signals including timing pulses and data pulses; oscillator means for generating clocking pulses, the frequency of said clocking pulses being greater than the frequency of said timing pulses; first counting means selectively driven by said pulse train of electrical signals and by said clocking pulses, means responsive to said first counting means deriving a first count representative of the number of initial pulses to be ignored for resetting said first counting means and transferring the control thereof to said clocking pulses; means responsive to said first counting means when under the control of said clocking pulses for generating a first signal representative of any pulse in said pulse train; means for decoding said first counter means when under the control of said clocking pulses for generating for each timing pulse in said signal train first, second, third, and fourth control signals in time sequential fashion; second counting means for registering a second count representing the time between adjacent timing pulses in said signal train; third counting means; loading means responsive to said second control signal for conditioning said third counting means to count said second number; means for causing said third counter to count said second number at a faster rate than said second counter; said third counting means providing a fifth control signal upon counting said second number; latch means for registering as a data pulse a pulse occurring in said signal train before provision of said fifth control signal, means responsive to said first control signal for resetting said third counter, means responsive to said third control signal for resetting said second counter, means responsive to said fourth control signal for conditioning said latch means to register a subsequent data pulse; whereby data pulses in said pulse train are detected as those occurring after a timing pulse within a time that represents a fraction of the time between that timing pulse and the next preceding timing pulse where the time between timing pulses is subject to wide variations.
 5. In a pulse train decoding system, apparatus for generating control signals comprising: means for generating a signal train of electrical signals; oscillator means for generating electrical clocking signals, the frequency of said clocking signals being greater than the frequency of said signal train; counting means selectively driven by said signal train and by said clocking signals; means responsive to said counting means deriving a count representative of the number of initial signals in said signal train to be ignored for resetting said counting means and transferring control thereof to said clocking signals; and means for decoding said counting means when under control of said clocking signals for generating a plurality time sequential control signals.
 6. Apparatus for decoding a signal train of double frequency encoded electrical signals, including timing and information signals, comprising: means for generating high frEquency electrical clocking signals, first dividing means responsive to said clocking signals for generating second clocking signals; second dividing means responsive to said clocking signals for generating third clocking signals, said third clocking signals having a higher frequency than said second clocking signals; first unidirectional counting means responsive to said second counting signals for generating a count representing the time between adjacent timing signals; second unidirectional counting means responsive to said third counting signals for generating said count and, thereupon, providing a control signal, detecting means responsive to said control signal for detecting the next timing signal in said signal train and the presence or absence of an information signal. 